Cache memory is a standard feature on modern processors, permitting faster access to data as compared to accessing the main memory (RAM). However, in multiprocessor systems, cache coherency is an issue, as cache memory associated with each processor has access to a common memory resource, giving rise to the potential for discrepancies in the data stored in different caches. Multiprocessor systems conventionally guarantee cache coherency using a variety of protocols such as the MESI protocol (Modified: Exclusive: Shared: Invalid). The purpose of such protocols is to ensure that a processor has exclusive access to a memory location for performing a read or write operation.
If two or more processors write to the same memory location, each processor needs to wait for one additional memory cycle, being the cycle that validates and invalidates other processor caches. This potentially creates a ‘ping-pong’ scenario, so that accessing cached memory becomes slower than uncached memory access. The overheads for ensuring exclusive access on systems such as NUMA (Non-Uniform Memory Access) are even greater. One solution to this problem is to prevent such memory pages from being cached. However, this solution has its own drawbacks. For example, hyper threading processors may share caches, even at the cache level that is closest to the processor.
Another problem in conventional systems which is similar to the ping-pong scenario is that of false cache sharing. This may, for example, occur where different data items are always loaded into the same cache line, but each of two or more processors require concurrent access to the items.
Yet another problem with cache control in conventional systems is that an application's important cache-sensitive data may be overwritten by its own access to other less important data, or by accesses to other data made by less important applications.